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PHU97NQ03LT
N-channel TrenchMOS logic level FET
Rev. 01 -- 25 February 2008 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
1.2 Features
I Logic level threshold I Low on-state resistance I Fast switching I Lead-free packing
1.3 Applications
I DC-to-DC converters I Voltage regulators I Switched-mode power supplies I Computer motherboards
1.4 Quick reference data
I VDS 25 V I RDSon 6.6 m I ID 75 A I QGD = 1.9 nC (typ)
2. Pinning information
Table 1. Pin 1 2 3 mb Pinning Description gate (G) drain (D) source (S) mounting base; connected to drain (D)
mbb076
Simplified outline
mb
Symbol
D
G S
1
2
3
SOT533 (IPAK)
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2. Ordering information Package Name PHU97NQ03LT IPAK Description plastic single-ended package (IPAK); 3 leads (In-line) Version SOT533 Type number
4. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 35 A; tp = 0.1 ms; VDS 25 V; RGS = 50 ; VGS = 10 V; starting at Tj = 25 C Tmb = 25 C; VGS = 10 V; see Figure 2 and 3 Tmb = 100 C; VGS = 10 V; see Figure 2 Tmb = 25 C; pulsed; tp 10 s; see Figure 3 Tmb = 25 C; see Figure 1 Conditions 25 C Tj 175 C 25 C Tj 175 C; RGS = 20 k Min -55 -55 Max 25 25 20 75 69 300 107 +175 +175 75 240 60 Unit V V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
2 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
120 Pder (%) 80
003aab844
120 Ider (%) 80
003aab533
40
40
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 Tj (C) 200
P tot P der = ----------------------- x 100 % P tot ( 25C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature
103 ID (A) 102
ID I der = ------------------- x 100 % I D ( 25C ) Fig 2. Normalized continuous drain current as a function of mounting base temperature
003aab556
RDSon = VDS / ID
tp = 10 s
100 s DC 10 1 ms 10 ms
1 10-1
1
10 VDS (V)
102
Tmb = 25 C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
3 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4. Rth(j-mb) Rth(j-a)
[1]
Thermal characteristics Conditions
[1]
Symbol Parameter thermal resistance from junction to ambient
Min -
Typ 70
Max 1.4 -
Unit K/W K/W
thermal resistance from junction to mounting base see Figure 4
Vertical in still air; SOT533 package.
10 Zth(j-mb) (K/W) 1
003aab535
= 0.5 0.2 0.1
P = tp T
10-1
0.05 0.02
single pulse
tp t T
10
-2
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
4 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5. Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain leakage current VDS = 25 V; VGS = 0 V Tj = 25 C Tj = 175 C IGSS RG RDSon gate leakage current gate resistance drain-source on-state resistance VGS = 16 V; VDS = 0 V f = 1 MHz VGS = 10 V; ID = 25 A; see Figure 6 and 8 Tj = 25 C Tj = 175 C VGS = 4.5 V; ID = 25 A; see Figure 6 and 8 Dynamic characteristics QG(tot) QGS QGS1 QGS2 QGD VGS(pl) Ciss Coss Crss Ciss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge pre-VGS(th) gate-source charge post-VGS(th) gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance input capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; see Figure 13 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V VGS = 0 V; VDS = 0 V; f = 1 MHz VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG = 5.6 VGS = 0 V; VDS = 12 V; f = 1 MHz; see Figure 14 ID = 25 A; VDS = 12 V; VGS = 4.5 V; ID = 0 A; VDS = 0 V; VGS = 4.5 V see Figure 11 and 12 11.7 10.2 6.2 3.4 2.8 1.9 3.1 1570 380 160 1800 18 33 20 12 0.87 38 14 1.2 nC nC nC nC nC nC V pF pF pF pF ns ns ns ns V ns nC 5.6 10.4 8.3 6.6 12.3 10.9 m m m 1.5 1 100 100 A A nA 1.3 0.7 1.7 2.15 2.6 V V V 25 22 V V Conditions Min Typ Max Unit
Source-drain diode
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
5 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
80 ID (A) 60
003aab536
10
6
5
4.5
4.1 3.7
25 RDSon (m) 20 VGS (V) = 3.3
003aab537
15 40 3.3 10 20 2.9 5 VGS (V) = 2.5 0 0 0.2 0.4 0.6 0.8 VDS (V) 1 0 0 20 40 60
3.7
4.1 4.5 5 6 10
ID (A)
80
Tj = 25 C
Tj = 25 C
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values
80 ID (A) 60
003aac094
Fig 6. Drain-source on-state resistance as a function of drain current; typical values
2 a 1.6
003aab467
1.2 40 0.8 20 Tj = 175 C 25 C 0.4
0 0 1 2 3 VGS (V) 4
0 -60
0
60
120 Tj (C)
180
Tj = 25 C and 175 C; VDS > ID x RDSon
R DSon a = ----------------------------R DSon ( 25C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature
Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
6 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
2.5 VGS(th) (V) 2.0 max
003aab986
10-1 ID (A) 10-2
003aab938
1.5
typ
10-3 min 10-4 typ max
1.0
min
0.5
10-5
0.0 -60
10-6 0 60 120 Tj (C) 180 0 1 2 VGS (V) 3
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature
10 VGS ID = 25 A Tj = 25 C (V) 8
003aab539
Fig 10. Sub-threshold drain current as a function of gate-source voltage
VDS ID
6 12 V
VDS = 19 V
VGS(pl)
4
VGS(th)
2
VGS QGS1 QGS2 QGD QG(tot)
003aaa508
QGS
0 0 10 20 QG (nC) 30
ID = 25 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Gate charge waveform definitions
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
7 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
80 IS (A) 60
003aab541
104 C (pF)
003aab542
Ciss 40 10
3
175 C 20
Tj = 25 C Coss
Crss 0 0 0.4 0.8 VSD (V) 1.2 102 10-1 1 10 VDS (V) 102
Tj = 25 C and 175 C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain voltage; typical values
Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
8 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended package (IPAK); 3 leads (in-line) SOT533
E E1 A1
A
D1 mounting base D2
L1 Q
L
1
2
3
e1 e
b
w
M
c
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 c 0.56 0.46 D1 1.10 0.96 D2 6.22 5.98 E 6.73 6.47 E1 e e1 L 9.6 9.2 L1 (2) max 2.7 Q 1.1 1.0 w 0.3
2.285 5.21 4.57 5.00 BSC (1) BSC (1)
Notes 1. Basic spacing between centers. 2. Terminal dimensions are uncontrolled within zone L1. OUTLINE VERSION SOT533 REFERENCES IEC JEDEC TO-251 JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-02-14
Fig 15. Package outline SOT533 (IPAK)
PHU97NQ03LT_1 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
9 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 6. Revision history Release date 20080225 Data sheet status Product data sheet Change notice Supersedes Document ID PHU97NQ03LT_1
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
10 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PHU97NQ03LT_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 25 February 2008
11 of 12
NXP Semiconductors
PHU97NQ03LT
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 February 2008 Document identifier: PHU97NQ03LT_1

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